ddu12h doc #97036 data delay devices, inc. 1 12/11/97 3 mt. prospect ave. clifton, nj 07013 5-tap, ecl-interfaced fixed delay line (series ddu12h) features packages ten equally spaced outputs fits in 300 mil 32-pin dip socket input & outputs fully 10kh-ecl interfaced & buffered functional description the ddu12h-series device is a 10-tap digitally buffered delay line. the signal input (in) is reproduced at the outputs (t1-t10), shifted in time by an amount determined by the device dash number (see table). for dash numbers less than 20, the total delay of the line is measured from t1 to t10. the nominal tap-to-tap delay increment is given by one-ninth of the total delay, and the inherent delay from in to t1 is nominally 1.5ns. for dash numbers greater than or equal to 20, the total delay of the line is measured from in to t10. the nominal tap-to-tap delay increment is given by one-tenth of this number. series specifications minimum input pulse width: 10% of total delay output rise time: 2ns typical supply voltage: -5vdc 5% power dissipation: 400mw typical (no load) operating temperature: -30 to 85 c temp. coefficient of total delay: 100 ppm/ c 10% 10% 10% 10% vcc gnd in t1 t2 t3 t4 t10 functional diagram for dash numbers < 20 1.5ns 10% 10% 10% 10% t5 t6 t7 t8 10% t9 10% 10% 10% 10% vcc gnd in t1 t2 t3 t4 t10 functional diagram for dash numbers >= 20 10% 10% 10% 10% t5 t6 t7 t8 10% t9 10% 1997 data delay devices data delay devices, inc. 3 32 31 30 29 24 23 22 21 1 3 4 5 8 9 11 12 16 gnd t2 t4 in vee gnd t2 t4 vee gnd t1 t3 t5 gnd t6 t8 t10 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 gnd t2 t4 in n/c vee gnd n/c n/c t7 t8 vee gnd t1 t3 t5 n/c n/c gnd n/c n/c t6 t8 t10 ddu12h-xx dip ddu12h-xxm military dip ddu12h-xxc3 smd ddu12h-xxmc3 mil smd pin descriptions in signal input t1-t10 tap outputs vee -5 volts gnd ground dash number specifications part number total delay ( ns) delay per tap ( ns) ddu12h-10 9 1.0 * 1.0 0.3 ddu12h-20 20 2.0 2.0 0.4 ddu12h-25 25 2.0 2.5 0.4 ddu12h-40 40 2.0 4.0 0.5 ddu12h-50 50 2.5 5.0 1.0 ddu12h-75 75 4.0 7.5 1.5 ddu12h-100 100 5.0 10.0 2.0 ddu12h-150 150 7.5 15.0 2.0 ddu12h-200 200 10.0 20.0 2.0 ddu12h-250 250 12.5 25.0 2.0 ddu12h-300 300 15.0 30.0 2.0 ddu12h-400 400 20.0 40.0 2.0 ddu12h-500 500 25.0 50.0 2.5 ddu12h-750 750 37.5 75.0 4.0 ddu12h-1000 1000 50.0 100.0 5.0 ddu12h-1500 1500 75.0 150.0 7.0 * total delay is referenced to first tap output input to first tap = 1.5ns 1ns note: any dash number between 10 and 1500 not shown is also available.
ddu12h doc #97036 data delay devices, inc. 2 12/11/97 tel: 973-773-2299 fax: 973-773-9672 http://www.datadelay.com application notes high frequency response the ddu12h tolerances are guaranteed for input pulse widths and periods greater than those specified in the test conditions. although the device will function properly for pulse widths as small as 10% of the total delay and periods as small as 20% of the total delay (for a symmetric input), the delays may deviate from their values at low frequency. however, for a given input condition, the deviation will be repeatable from pulse to pulse. contact technical support at data delay devices if your application requires device testing at a specific input condition. power supply bypassing the ddu12h relies on a stable power supply to produce repeatable delays within the stated tolerances. a 0.1uf capacitor from vee to gnd, located as close as possible to the vee pin, is recommended. a wide vee trace and a clean ground plane should be used. device specifications table 1: absolute maximum ratings parameter symbol min max units notes dc supply voltage v ee -7.0 0.3 v input pin voltage v in v ee - 0.3 0.3 v storage temperature t strg -55 150 c lead temperature t lead 300 c 10 sec table 2: dc electrical characteristics (0c to 75c) parameter symbol min typ max units notes high level output voltage v oh -1.020 -0.735 v v ih = max,50 w to -2v low level output voltage v ol -1.950 -1.600 v v il = min, 50 w to -2v high level input voltage v ih -1.070 v low level input voltage v il -1.480 v high level input current i ih 475 m a v ih = max low level input current i il 0.5 m a v il = min
ddu12h doc #97036 data delay devices, inc. 3 12/11/97 3 mt. prospect ave. clifton, nj 07013 package dimensions ddu12h-xx (commercial dip) ddu12h-xxm (military dip) .150 .030 1.650 typ. 1 3 4 5 8 16 12 11 9 .320 max. .018 typ. .400 typ. .300 typ. .012 typ. .020 typ. 29 30 31 32 21 22 23 24 .100 .200 .300 .400 .700 .800 .900 1.000 1.100 1.500 .075 ddu12h-xxc4 (commercial smd) ddu12h-xxmc4 (military smd) 1.280 .020 .882 .005 .020 typ. .040 typ. .100 .090 1.100 .280 max. .590 max. .010 .002 .050 .010 .710 .005 .007 .005 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
ddu12h doc #97036 data delay devices, inc. 4 12/11/97 tel: 973-773-2299 fax: 973-773-9672 http://www.datadelay.com delay line automated testing test conditions input: output: ambient temperature: 25 o c 3 o c load: 50 w to -2v supply voltage ( vcc): -5.0v 0.1v c load : 5pf 10% input pulse: standard 10kh ecl threshold: (v oh + v ol ) / 2 levels (rising & falling) source impedance: 50 w max. rise/fall time: 2.0 ns max. (measured between 20% and 80%) pulse width: pw in = 1.5 x total delay period: per in = 10 x total delay note: the above conditions are for test only and do not in any way restrict the operation of the device. t1 out trig in ref trig test setup device under test (dut) oscilloscope pulse generator in t2 t3 t4 t5 t6 t7 t8 t9 t10 timing diagram for testing t rise t fall per in pw in t rise t fall 20% 20% 50% 50% 80% 80% 50% 50% v ih v il v oh v ol input signal output signal
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